1. Field of the Invention
The present invention relates to a parallel computer system including processing elements. More specifically, the present invention relates to a parallel computer system which is provided with a plurality of processing elements and data is sent and received between the processing elements in accordance with a processing element number assigned to each processing element.
2. Description of the Prior Arts
Recently, researches are advanced toward realization of a practical parallel computer. Especially, as advancement of a semiconductor technology, there are researches in which a communication control unit and a data processing unit are implemented as a processing element of a single-chip LSI and a large number of such processing element LSIs are connected to realize a parallel computer.
For example, in a parallel computer disclosed in pages 181-218 of "Nikkei Electronics" issued on Apr. 9, 1984, a data communication system in which a plurality of single-chip processing elements called as ImPP (Image Pipelined Processor) are connected in a ring manner to send and receive the data.
In addition, as disclosed in pages 1048-1049 of a collection of papers 2T-2 for the 38th national meeting (the first half year in 1989) of the Information Processing Society, the inventors et al. are advancing development of a large-scale parallel data driven computer EDDEN (Enhanced Data Driven ENgine) wherein a maximum of 1024 processing elements each of which is incorporated in a single chip are connected.
In such a parallel computer, generally, a processing element number is assigned to each of the processing elements to identify respective processing elements and the number (addressing number) of the processing element to which communication data is to be sent is added to the communication data. In each processing element, the addressing number included in the communication data arrived at a network control unit and its own processing element number are compared with each other and, if the both are coincident with each other, the communication data is fetched in a data processing unit.
In order to implement a data communication system in such a parallel computer, first, it is necessary to provide with a function for setting processing element numbers into respective processing elements. For example, in the aforementioned processing element called as ImPP, a method in which a module number indicated by 4 bits is set by means of a module setting buffer externally connected to the LSI is adopted (see FIG. 14 in page 206 of "Nikkei Electronics").
In such a case, since pins for data signals of the LSI are also used for setting the module number, it is necessary to connect an external circuit including a tri-state buffer, dip switch and etc. to each of the processing element chip. However, in each processing element chip, it is possible to separately provide with pins for setting the module number and pins for data signals. In this case, the above described tri-state buffer becomes unnecessary, but the total number of pins of the processing element LSI increases.
However, in the parallel computer system in which a large number of processing elements are connected as the aforementioned EDDEN, since a size of an LSI package of one processing element, a scale of the external circuit and etc. have a great influence on a size of a whole system, it is desired that the total number of pins of the LSI is made small and the scale of the external circuit is miniaturized as much as possible.
In addition, in the above described method wherein the processing element number is directly set from the outside to each of the processing element LSIs, if change of the processing element number become needed, all the dip switches corresponding to all the processing elements must be operated to change the processing element numbers, and thus, an extensive working amount becomes necessary.